1. Technical Field
The present invention relates to integrated circuit technology and, in particular, to testing and diagnostics in a scan design. Still more particularly, the exemplary embodiments of the present invention provide a method and apparatus for diagnosing broken scan chains based on leakage light emission.
2. Description of Related Art
It is common for integrated circuit (IC) technology to use scan-based design methodologies and techniques to facilitate design, testing, and diagnostics. In scan design, especially full scan design, sequential circuits are converted into combinational circuits via scannable latches or flip-flops during testing. Using a scan-based design, structural testing may be more controllable and observable. Another aspect of using scan design is that the test cost is less than functional testing, especially for submicron designs.
FIG. 1 is a block diagram of a typical level-sensitive scan design (LSSD) circuit structure. Inputs are received by combinational logic 110 and the outputs of combinational logic 110 are received by scan chain latches 120. The outputs of scan chain latches 120 are controlled by scan clocks, system clocks, and scan register inputs (SRI).
The outputs of scan chain latches 120 are then provided to combinational logic 130 in the next level of the LSSD circuit structure. In turn, outputs from combinational logic 130 are received by scan chain latches 140. Scan register outputs (SRO) are provided from scan chain latches 120 to scan chain latches 140. The outputs of scan chain latches 140 are then provided to combinational logic 150 in the next level of the LSSD circuit structure. The outputs of combinational logic 150, as well as the scan register outputs from scan chain latches 140, are provided as outputs of the LSSD circuit.
A defect in an LSSD circuit structure may reside in combinatorial logic or in the scan latches. Thus, it becomes difficult to locate the exact location of the defect. For this reason, the scan chain itself may be analyzed to determine whether a defect exists in the scan chain. A scan chain may be broken if a wire is broken or shorted or if a component within a latch or clock buffer is not functioning properly. Problems in the scan chain must be corrected before the combinatorial logic may be analyzed.
FIG. 2 depicts a schematic diagram of an example LSSD scan chain configuration. Scan register input is received by a first set of latches. Each L1 latch receives scan register input and two clock signals, a-clk and c1-clk. Each L2 latch receives the output of the L1 latch and clock input b-clk. During a scan test, the c1-clk clock is not run, because the test is not concerned with data from the logic, only the function of the scan chain. The levels in the scan chain design are delineated by a plurality of shift, or scan, register latches (SRL).
If the scan chain is not working or is defective, scan chain diagnostics should be performed. In other words, the exact defect location should be localized. Scan diagnostics becomes important with shrinking lithography and increasing chip size, because more and more latches are added to new designs and this trend will continue. For example, the IBM G6 S/390 microprocessor in 1999 had about 76,000 scannable latches and the latest IBM S/390 zSeries 900 microprocessor in 2001 had more than 110,000 scannable latches. In some cases, these latches occupy as much as 30% of the overall chip area. As a result, about 10% to 30% of defects that occur on a whole chip may cause the scan chain to fail. Therefore, rapidly identifying the defect type of the scan chain may significantly improve the overall manufacturing yield.
Several scan diagnostics methods have been proposed in the past decade. Schafer et al., “Partner SRLs for Improved Shift Register Diagnostics,” IEEE VLSI Test Symposium, pp. 198-201, 1992, introduces a reconfiguration of the scan chain for scan chain diagnostic purposes. A stuck-at fault on a scan chain can be captured in the partner shift register latches. The limitation is that both the shift register and the associated partner shift register cannot be defective at the same time. Narayanan et al., “An Efficient Scheme to Diagnose Scan Chain,” Proc. International Test Conference, pp. 704-713, 1997, proposes modifying the existing scannable flop to add set/reset capability. Therefore, a broken scan chain may be easily diagnosed. Similarly, Wu, “Diagnosis of Scan Chain Failures,” Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 217-222, 1998, proposes adding some overhead to the scan flops in order to flip or set/reset the scan flip-flops. A bidirectional scan chain design is proposed in Song, “A New Scan Structure for Improving Scan Chain Diagnosis and Delay Fault Coverage,” 9th IEEE North Atlantic Test Workshop, pp. 14-18, 2000, where the scan fault can be diagnosed by performing both forward and backward scan tests. In Song et al., “Scan Structure for Improving Transition Fault Coverage and Scan Diagnostics,” U.S. Pat. No. 6,490,702, December 2002, a modified scan chain is proposed for accurate scan chain diagnostics.
Not only the scan chain may be diagnosed with added hardware, but software may also be used for diagnosis. Kundu, “On Diagnosis of Faults in a Scan Chain,” IEEE VLSI Test Symposium, pp. 303-308, 1993, introduces the use of a sequential automatic test pattern generator (ATPG) technique that diagnoses faults in a scan chain. In Stanley, “High Accuracy Fault and Scan Software Diagnostic,” 1st IEEE Workshop on Field Optimization & Test, 2000, a fault simulation and matching algorithm are used to find the best scan fault candidates. In Guo et al., “A Technique for Fault Diagnosis of Defects in Scan Chain,” Proc. International Test Conference, pp. 268-277, 2001, the ATPG patterns are applied to identify the range of suspect scan chain and further to simulate the faults in the suspect range for resolution purposes. The above approaches rely on extensive fault simulation and a large amount of data collection. These approaches also assume that the logic between scan chains is fault free.